Semiconductor device

ABSTRACT

A contact plug  26  formed between adjacent two wirings  14  according to a self-aligning manner is provided. An interlayer oxide film  12  is provided on a substrate layer  10  conductive to the bottom face of the contact plug. A lower insulating film  32  formed of a nitride based insulating film is provided so as to cover the entire surface of the interlayer oxide film  12  except for the contact hole portion. A wiring  12 , an upper insulating film  16  formed of a nitride based insulating film, and sidewalls  18  formed of a nitride based insulating film are provided over the lower insulating film  32.  The contact hole has a diameter larger than the interval defined between the wirings  14  in the same layer as the interlayer oxide film  12.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and moreparticularly to a semiconductor device having a contact hole defined bya self-aligning manner.

2. Description of the Background Art

With an improvement in integration of a semiconductor device and thescaling-down of a memory cell, difficulties have recently beenencountered in defining a contact between adjacent wirings withoutdeveloping a short circuit in wiring. A technique called a self-aligningmanner has heretofore been used as one method for defining a contacthole while preventing a short circuit developed in wiring.

FIGS. 1A through 1F respectively show a series of cross-sectional viewsfor describing a conventional method of defining a contact hole by usinga self-aligning manner. According to the conventional method, aninterlayer oxide film 12 is first deposited on a semiconductor substrate10 as shown in FIG. 1A. A silicon film 14 is deposited on the interlayeroxide film 12 and a nitride film 16 for protecting the silicon film 14is further deposited thereon.

Next, the silicon film 14 and the nitride film 16 are patterned indesired wiring form as shown in FIG. 1B.

Afterwards, sidewalls 18 for protecting the side faces of each siliconfilm 14 are formed by a nitride film as shown in FIG. 1C. Each siliconfilm 14 patterned in wiring form is brought to a state of being coveredwith the nitride film at this stage.

After the sidewalls 18 have been formed, an interlayer oxide film 20 isdeposited over the entire surface of a semiconductor wafer as shown inFIG. 1D. Next, a predetermined heat treatment is carried out to enhancethe embedding characteristics and flatness of the interlayer oxide film20.

As shown in FIG. 1E, a photoresist 22 is patterned onto the interlayeroxide film 20. Oxide-film etching for defining a contact hole 24 isexecuted with the photoresist 22 as a mask. This etching is carried outunder a condition for removing an oxide film at a higher selectivitythan that for the nitride film. Since, in this case, each of the nitridefilm 16 and sidewalls 18 functions as a stopper film for stopping theprogress of the etching, the contact hole 24 can be defined up to thesemiconductor substrate 10 without exposing each wiring to the inside ofthe contact hole 24 even when a opening of the photoresist 22 is widerthan the interval between the wirings. A technique for defining thecontact hole in place on a self-alignment basis in this way is called a“self-aligning manner”.

The photoresist 22 is removed after the contact hole 24 has beendefined. A silicon film is deposited over the entire surface of asemiconductor wafer so that the contact hole 24 is filled with silicon.The so-deposited silicon is patterned in desired shapes, so that such acontact plug 26 and a wiring 28 as shown in FIG. 1F are formed.

In the aforementioned conventional method, the etching for defining thecontact hole 24 is carried out under the circumstances in which the sidefaces of each silicon film 14 patterned in wiring form have been coveredwith the sidewalls 18. In this case, the width of the contact hole 24 inthe vicinity of a lower end thereof becomes narrower than the intervaldefined between the adjacent two sidewalls 18. According to the etchingfor defining the contact hole 24 by which an oxide film isanisotropically etched at a higher selectivity than that for the nitridefilm, the interlayer oxide film 12 located below the sidewalls 18 isetched in tapered form.

As a result, the diameter of the bottom of the contact hole 24 becomesdrastically smaller than the interval defined between the adjacentsilicon films 14, i.e., the interval defined between the wirings.Therefore, the conventional method is apt to cause problems such as anincrease in contact resistance, degradation of drive capability of atransistor.

As a technique for solving the above problems, it can be usedillustratively a method in which the contact hole 24 is defined by dryetching, and thereafter HF-system wet etching or the like is carried outto thereby retreat the interlayer oxide film 12.

However, as shown in FIG. 2, such wet etching may cause exposed portions30 formed at parts of the bottoms of silicon films 14 so as to beexposed inside the contact hole 24. In this configuration, a shortcircuit would be developed between each silicon film 14 and the contactplug 26 which is formed inside the contact hole 24.

SUMMARY OF THE INVENTION

The present invention has been made to solve the above problems. Anobject thereof is to provide a semiconductor device having a contacthole whose bottom is scaled up, and a structure suited to prevent ashort circuit from arising between a wiring and a contact plug.

The above objects of the present invention are achieved by asemiconductor device described below. The semiconductor device includesa contact hole defined between adjacent two wirings by a self-aligningmanner. A contact plug is formed in the contact hole. A substrate layeris provided so as to be conductive to the bottom face of the contactplug. An interlayer oxide film is formed on the substrate layer. A lowerinsulating film formed of a nitride based insulating film is provided soas to cover the entire surface of the interlayer oxide film except forthe contact hole portion. The two wirings are formed on the lowerinsulating film with the contact hole interposed therebetween. An upperinsulating film formed of a nitride based insulating film is providedwith the same width as the each wiring so as to cover the upper surfaceof the each wiring. The semiconductor device also includes sidewallsformed of a nitride based insulating film so as to cover the side facesof the each wiring and the side faces of the upper insulating film. Thecontact hole has an enlarged portion formed in the same layer as theinterlayer oxide film, which has a diameter larger than an intervaldefined between the two wirings.

The above objects of the present invention are also achieved by asemiconductor device described below. The semiconductor device includesa contact hole defined between adjacent two wirings by a self-aligningmanner. A contact plug is formed in the contact hole. A substrate layeris provided so as to be conductive to the bottom face of the contactplug. An interlayer oxide film is formed on the substrate layer. The twowirings are formed in a layer above the interlayer oxide film with thecontact hole interposed therebetween. A lower insulating film formed ofa nitride based insulating film is provided between the interlayer oxidefilm and the each wiring with the same width as the each wiring. Anupper insulating film formed of a nitride based insulating film isprovided so as to cover the upper surface of the each wiring with thesame width as the each wiring. The semiconductor device also includessidewalls formed of a nitride based insulating film so as to cover theside faces of the each wiring and the side faces of the upper and lowerinsulating films. The contact hole has a diameter larger than aninterval defined between the two wirings within the same layer as theinterlayer oxide film. The bottom face of the each sidewall is shiftedtoward the substrate layer by a predetermined length as compared withthe bottom face of the lower insulating film.

The above objects of the present invention are further achieved by asemiconductor device described below. The semiconductor device includesa contact hole defined between adjacent two wirings by a self-aligningmanner. A contact plug is formed in the contact hole. A substrate layeris provided so as to be conductive to the bottom face of the contactplug. An interlayer oxide film is formed on the substrate layer The twowirings are formed on the interlayer oxide film with the contact holeinterposed therebetween. An upper insulating film formed of a nitridebased insulating film is provided so as to cover the upper surface ofthe each wiring with the same width as the wiring. Sidewalls formed of anitride based insulating film are provided so as to cover the side facesof the each wiring and the side faces of the upper insulating film. Thesemiconductor device also includes a short-circuit proof film formed ofa single insulating material so as to cover the entire side face of thecontact plug. The contact hole has a diameter larger than an intervaldefined between the two wirings within the same layer as the interlayeroxide film.

Other objects and further features of the present invention will beapparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1F are cross-sectional views for describing a conventionalmanufacturing method;

FIG. 2 is a view for describing problems developed where the technologyof enlarging a contact hole is applied to the conventional manufacturingmethod;

FIGS. 3A to 3H are cross-sectional views for describing a manufacturingmethod according to a first embodiment of the present invention;

FIGS. 4A to 4G are cross-sectional views for describing a manufacturingmethod according to a second embodiment of the present invention;

FIGS. 5A to 5G are cross-sectional views for describing a manufacturingmethod according to a third embodiment of the present invention;

FIGS. 6A to 6I are cross-sectional views for describing a manufacturingmethod according to a fourth embodiment of the present invention;

FIG. 7 is a plan view for describing a structure of a semiconductordevice according to a firth embodiment of the present invention;

FIGS. 8A to 9F are cross-sectional views for describing a manufacturingmethod according to the fifth embodiment of the present invention;

FIGS. 10A to 10D are cross-sectional views for describing amanufacturing method according to a sixth embodiment of the presentinvention;

FIGS. 11A to 11D are cross-sectional views for describing amanufacturing method according to a seventh embodiment of the presentinvention;

FIGS. 12A to 12F are cross-sectional views for describing amanufacturing method according to an eighth embodiment of the presentinvention;

FIG. 13 is a cross-sectional view of a memory cell at the time that anetching step for defining a bit line contact hole is started in themanufacturing method according to the fifth embodiment of the presentinvention; and

FIG. 14 is a cross-sectional view of a memory cell at the time that anetching step for defining a bit line contact hole is started in amanufacturing method according to a ninth embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

A first embodiment of the present invention will be explained below withreference to FIGS. 3A through 3H. Elements common in respective drawingsare identified by the same reference numerals and the description of thecommon elements will therefore be omitted.

In a manufacturing method of the present embodiment, an interlayer oxidefilm 12 is first formed on a semiconductor substrate 10 as shown in FIG.3A. The interlayer oxide film 12 is formed by a reduced pressure oratmospheric pressure CVD method to a thickness of from 50 nm to 100 nmso as to contain no impurities.

A nitride film 32 is formed on the interlayer oxide film 12 with athickness of from 20 nm to 100 nm. The film to be formed on theinterlayer oxide film 12 may be a film capable of securing enoughselectivity with respect to a silicon oxide film upon dry etching.Either a nitride oxide film or a laminated film of a nitride film and anitride oxide film may be used as an alternative to the nitride film 32.

A silicon film 14 is formed on the nitride film 32 with a thickness of50 nm to 200 nm. The silicon film 14 is a doped silicon film ofpolycrystalline silicon or amorphous silicon deposited by a CVD methodand contains an impurity such as P or As or the like. The film to beformed on the nitride film 32 maybe a conductive film. As an alternativeto the silicon film 14, a silicide film including a high melting pointmetal film such as Ti, TiN or W or the like, a laminated film of a dopedsilicon film and a silicide film, or a conductive metal film such as W,Al may be used.

A nitride film 16 is deposited on the silicon film 14. A thickness of 20nm to 100 nm is provided for the nitride film 16 in a manner similar tothe nitride film 32. In the present embodiment, a nitride oxide film, alaminated film of a nitride film and a nitride oxide film or the likemay be substituted for the nitride film 16.

Dry etching such as a RIE method is carried out with an unillustratedphotoresist as a mask to thereby pattern the nitride film 16 and thesilicon film 14 in desired wiring shapes as shown in FIG. 3B. At thistime, the dry etching is stopped at a stage in which the removal of thenitride film 32 advances midway, i.e., at the stage is which the nitridefilm 32 remains over the entire surface of a semiconductor wafer.

Next, a silicon nitride film is deposited over the entire surface of thesemiconductor wafer with a thickness of 20 nm to 80 nm. The overallsurface of the semiconductor wafer is etched back by dry etching such asthe RIE method, whereby sidewalls 18 for covering the side faces of eachsilicon film 16 are formed as shown in FIG. 3C. The above etchback isfinished before the nitride film 32 is perfectly removed. Thus, thenitride film 32 remains over the entire surface of the semiconductorwafer after the completion of the etchback.

After the above-described etch back, an interlayer oxide film 20 isdeposited over the entire surface of the semiconductor wafer as shown inFIG. 3D. The interlayer oxide film 20 is formed by depositing a siliconoxide film containing no impurity with a thickness of 500 nm to 1000 nmby the reduced pressure or atmospheric CVD method.

As an alternative to the non-doped silicon oxide film, a silicon oxidefilm doped with P or B may be deposited to form the interlayer oxidefilm 20. The embedding characteristics and flatness of the interlayeroxide film 20 can be enhanced by annealing the deposited silicon oxidefilm 20 in an H₂O, O₂ or N₂ atmosphere at a temperature within a rangeof 700° C. to 900° C. (reflow method).

The annealing in the H₂O or O₂ atmosphere rather than in the N₂atmosphere is efficient to enhance the embedding characteristics andflatness. However, since the lower portion of the silicon film 14 is indanger of oxidizing in the conventional manufacturing method, theannealing of the interlayer oxide film 20 has been carried out only inthe N₂ atmosphere. On the other hand, since the nitride film 32 isformed so as to cover the bottom face of the silicon film 14 and coverthe entire surface of the semiconductor wafer in the present embodiment,the silicon film 14 is not oxidized even if annealing is executed in theH₂O or O₂ atmosphere. Thus, according to the manufacturing method of thepresent embodiment, H₂O or O₂ gas can be used as an anneal gas wherebythe embedding characteristics and flatness of the interlayer oxide film20 can be improved sufficiently.

As shown in FIG. 3E, a photoresist 22 is patterned on the interlayeroxide film 20. The interlayer oxide film 20 is dry-etched by the RIEmethod or the like with the photoresist 22 as a mask to thereby define acontact hole 24. At this time, the above-described dry etching is doneunder the condition that the silicon oxide film can be removed at ahigher selectivity than that for the silicon nitride film. Therefore,each of the nitride films 16 and 32 and the sidewalls 18 serves as astopper film for stopping the progress of etching.

After the removal of the photoresist 22, the nitride film 32 exposed tothe bottom of the contact hole 24 and the interlayer oxide film 12located therebelow are next removed by dry etching such as the RIEmethod. As a result, the contact hole 24 is defined which reaches thesurface of the semiconductor substrate 10 as shown in FIG. 3F.

In the present embodiment as described above, the nitride film 32 iscapable of temporarily stopping the progress of etching in the processof defining the contact hole 24. Condition of the etching for definingthe contact hole 24 with satisfactory accuracy can be controlled easierin a case where the progress of the etching is once stopped by thestopper film than in a case where the contact hole 24 is completelyformed without stoppage of the etching. Therefore, according to themanufacturing method of the present embodiment, the contact hole 24 canbe formed with satisfactory accuracy under simple condition control ascompared with the case in which the nitride film 32, which functions asthe stopper film, does not exist.

Next, wet etching using HF or the like is executed. As a result, theinterlayer oxide film 12 is retreated as shown in FIG. 3G, whereby thediameter of the contact hole 24 is scaled up below the nitride film 32.The above-described wet etching is continued until the contact hole 24exceeds an area just below the sidewalls 18 and reaches an area justbelow the silicon film 14. Since the nitride film 32 is formed under thesilicon film 14 in the present embodiment, no part of the silicon film14 is exposed to the inside of the contact hole 24 even if the contacthole 24 is enlarged in this way.

Next, a silicon film is deposited over the entire surface of asemiconductor wafer so that the contact hole 24 is filled with silicon.The silicon film is polycrystalline silicon or amorphous silicon dopedwith P or As and has a thickness of 50 nm to 200 nm on the interlayeroxide film 20. The so-deposited silicon is patterned in a desired shapeby the dry etching such as the RIE method. As a result, a contact plug26 and a wiring 28 are formed as shown in FIG. 3H.

Since the diameter of the bottom of the contact hole 24 is enlarged asdescribed above in the present embodiment, a large contact area isensured between the contact plug 26 and the semiconductor substrate 10.Therefore, the manufacturing method according to the present embodimentis capable of sufficiently reducing a contact resistance between thecontact plug 26 and the semiconductor substrate 10 and effectivelypreventing problems such as an increase in contact resistance, areduction in drive capability of each transistor.

Since the silicon film 14 is not exposed to the inside of the contacthole 24 in the present embodiment as described above, the silicon film14 and the contact plug 26 can reliably be prevented from beingshort-circuited, regardless of the scale up of the contact hole 24.Thus, according to the manufacturing method of the present embodiment, asemiconductor device can stably be manufactured which is low in contactresistance and provides stable operating characteristics.

Second Embodiment

A second embodiment of the present invention will be explained belowwith reference to FIGS. 4A through 4G.

In the manufacturing method according to the present embodiment, alaminated film of an interlayer oxide film 12, a nitride film 32, asilicon film 14 and a nitride film 16 is first formed over asemiconductor substrate 10 as shown in FIG. 4A in a manner similar tothe first embodiment.

Dry etching such as a RIE method is carried out with an unillustratedphotoresist as a mask to thereby pattern the nitride film 16, thesilicon film 14 and the nitride film 32 in desired wiring shapes asshown in FIG. 4B. In this step, the dry etching is stopped at a stage inwhich the interlayer oxide film 12 has been etched so as to range fromabout 10 nm to about 50 nm in thickness. As a result, the nitride film32 remains only under the silicon film 16 patterned to each wiringshape, and a step of from 10 nm to 50 nm is formed so as to existbetween the bottom face of the nitride film 32 and each exposed surfaceof the interlayer oxide film 12.

Next, a silicon nitride film is deposited over the entire surface of asemiconductor wafer with a thickness of 20 nm to 80 nm. The overallsurface of the semiconductor wafer is etched back by dry etching such asthe RIE method, so that sidewalls 18 for covering the side faces of eachsilicon film 16 are formed as shown in FIG. 4C. At this stage, a step offrom 10 nm to 50 nm is formed between the bottom face of the nitridefilm 32 and the bottom face of each sidewall 18 in the presentembodiment.

After the above-described etchback, an interlayer oxide film 20 isdeposited over the entire surface of the semiconductor wafer as shown inFIG. 4D. Depositing a silicon oxide film containing no impurity with athickness of 500 nm to 1000 nm forms the interlayer oxide film 20 by areduced pressure or atmospheric CVD method.

As an alternative to the non-doped silicon oxide film, a silicon oxidefilm doped with P or B may be deposited to form the interlayer oxidefilm 20 in a manner similar to the first embodiment. In this case, theembedding characteristics and flatness of the interlayer oxide film 20can be enhanced by executing anneal (reflow method) in an H₂O, O₂ or N₂atmosphere. At the stage of the annealing referred to above, the nitridefilm 32 does not remain over the entire surface of the semiconductorwafer differently from the first embodiment. However, since the bottomface of the silicon film 14 is covered with the nitride film 32 even inthe case of the present embodiment, annealing is allowed in the H₂O orO₂ atmosphere. Therefore, the manufacturing method according to thepresent embodiment can also provide excellent embedding characteristicsand flatness for the interlayer oxide film 20 in a manner similar to thefirst embodiment.

As shown in FIG. 4E, a photoresist 22 is patterned over the interlayeroxide film 20. The interlayer oxide film 20 is dry-etched by the RIEmethod or the like with the photoresist 22 as a mask, thereby defining acontact hole 24 therein. Since, at this time, the dry etching is doneunder the condition that the silicon oxide film can be removed at ahigher selectivity than that for the silicon nitride film, each of thenitride film 16 and the sidewalls 18 functions as a stopper film fordiscontinuing the progress of the etching. Therefore, according to thedry etching described above, the contact hole 24 can be defined up tothe semiconductor substrate 10 without exposing each silicon film 14.

After the photoresist 22 has been removed, wet etching using HF or thelike is carried out. As a result, the interlayer oxide film 12 iswithdrawn as shown in FIG. 4F, whereby the diameter of the contact hole24 is scaled up below the sidewalls 18 and the nitride film 32. Theabove-described wet etching is continued until the contact hole 24exceeds an area just below the sidewalls 18 and reaches an area justunder the silicon film 14. Since the nitride film 32 is formed under thesilicon film 14 in the present embodiment, no part of the silicon film14 is exposed to the inside of the contact hole 24 even if the contacthole 24 is enlarged in this way.

L1 shown in FIG. 4F indicates the distance between the surface of thesemiconductor substrate 10 and the bottom face of the sidewall 18. Whenthe contact hole 24 is formed according to a self-aligning technique,the contact hole 24 is tapered at a portion corresponding to thedistance L1 as shown in FIG. 4E. Therefore, the distance L1 needs to bedesigned to such a distance as not to cause an open failure in thecontact hole 24.

On the other hand, L2 shown in FIG. 4F indicates the distance betweenthe surface of the semiconductor substrate 10 and the bottom face of thesilicon film 14. A capacitance arising between wiring and the substrate10 in a semiconductor device decreases as the surface of thesemiconductor substrate 10 and the bottom face of the silicon film 14are distant from each other. Thus, it is advantageous to increase thedistance L2 for the purpose of restraining the capacitance.

In the present embodiment as described above, the bottom face of eachsidewall 18 is lowered toward the semiconductor substrate 10 by about 10nm to about 50 nm as viewed from the bottom face of the nitride film 32.Therefore, according to the structure of the present embodiment, a largedifference can be ensured between the distance L1 and the distance L2 ascompared with the case in which the bottom face of each sidewall 18 andthe bottom face of the nitride film 32 are placed in the same height.Thus, the manufacturing method according to the present embodiment issuperior to the conventional manufacturing method or the manufacturingmethod according to the first embodiment in terms of the restraint onthe capacitance arising between wiring and the substrate 10.

Next, a silicon film is deposited over the entire surface of asemiconductor wafer so that the contact hole 24 is filled with silicon.The silicon film is polycrystalline silicon or amorphous silicon dopedwith P or As and has a thickness of 50 nm to 200 nm on the interlayeroxide film 20. The so-deposited silicon is patterned in a desired shapeby the dry etching such as the RIE method. As a result, a contact plug26 and a wiring 28 are formed as shown in FIG. 4G.

According to the manufacturing method of the present embodiment asdescribed above, the diameter of the bottom of the contact hole 24 canbe enlarged without exposing the silicon film 14 to the inside of thecontact hole 24. Thus, according to the manufacturing method of thepresent embodiment, a semiconductor device can stably be manufacturedwhich is low in contact resistance and provides stable operatingcharacteristics, in a manner similar to the first embodiment.

Third Embodiment

A third embodiment of the present invention will be explained below withreference to FIGS. 5A through 5G.

In a manufacturing method according to the present embodiment, alaminated film of an interlayer oxide film 12, a nitride film 32, asilicon film 14 and a nitride film 16 is first formed over asemiconductor substrate 10 as shown in FIG. 5A in a manner similar tothe first embodiment.

Dry etching such as a RIE method is carried out with an unillustratedphotoresist as a mask to thereby pattern the nitride film 16 and thesilicon film 14 in desired wiring shapes as shown in FIG. 5B. The dryetching mentioned above is finished at a stage in which a nitride film32 has been etched to its midpoint. As a result, the nitride film 32remains over the entire surface of a semiconductor wafer at this stage.

Next, a silicon nitride film is deposited over the entire surface of thesemiconductor wafer with a thickness of 20 nm to 80 nm. The overallsurface of the semiconductor wafer is etched back by dry etching such asthe RIE method, whereby sidewalls 18 for covering the side faces of eachsilicon film 14 are formed as shown in FIG. 5C. In the presentembodiment, the nitride film 32 remains at a lower portion of thesilicon film 14 and a lower portion of each sidewall 18 at this stage.

After the above-described etchback, an interlayer oxide film 20 isdeposited over the entire surface of the semiconductor wafer as shown inFIG. 5D. Depositing a silicon oxide film containing no impurity with athickness of 500 nm to 1000 nm forms the interlayer oxide film 20 by areduced pressure or atmospheric CVD method.

As an alternative to the non-doped silicon oxide film, a silicon oxidefilm doped with P or B may be deposited to form the interlayer oxidefilm 20 in a manner similar to the first of second embodiment. In thiscase, the embedding characteristics and flatness of the interlayer oxidefilm 20 can be enhanced by performing annealing (reflow method) in anH₂O, O₂ or N₂ atmosphere. At the stage of the annealing referred toabove, the nitride film 32 exists only at the lower portion of thesilicon film 14 and the lower portion of each sidewall 18 as distinctfrom the first or second embodiment. However, since the bottom face ofthe silicon film 14 is covered with the nitride film 32 even in the caseof the present embodiment, annealing is allowed in the H₂O or O₂atmosphere. Therefore, the manufacturing method according to the presentembodiment can also provide excellent embedding characteristics andflatness for the interlayer oxide film 20 as compared with the case inwhich the bottom face of the silicon film 14 is not covered with thenitride film 32.

As shown in FIG. 5E, a photoresist 22 is patterned over the interlayeroxide film 20. The interlayer oxide film 20 is dry-etched by the RIEmethod or the like with the photoresist 22 as a mask, thereby defining acontact hole 24 therein. Since, at this time, the dry etching is doneunder the condition that the silicon oxide film can be removed at ahigher selectivity than that for the silicon nitride film, each of thenitride film 16, the sidewalls 18 and the nitride film 32 functions as astopper film for stopping the progress of the etching. Therefore,according to the dry etching described above, the contact hole 24 can bedefined up to the semiconductor substrate 10 without exposing eachsilicon film 14.

After the photoresist 22 has been removed, wet etching using HF or thelike is carried out. As a result, the interlayer oxide film 12 isretreated as shown in FIG. 5F, whereby the diameter of the contact hole24 is enlarged at the lower portion of the sidewalls 18 and the nitridefilm 32. The above-described wet etching is continued until the contacthole 24 exceeds an area just below the sidewalls 18 and reaches an areajust below the silicon film 14. Since the nitride film 32 is formedunder the silicon film 14 in the present embodiment, part of the siliconfilm 14 is not exposed to the inside of the contact hole 24 even if thecontact hole 24 is enlarged in this way.

Next, a silicon film is deposited over the entire surface of thesemiconductor wafer so that silicon is charged into the contact hole 24.The silicon film is polycrystalline silicon or amorphous silicon dopedwith P or As and has a thickness of 50 nm to 200 nm on the interlayeroxide film 20. The so-deposited silicon is patterned in each desiredshape by the dry etching such as the RIE method. As a result, a contactplug 26 and a wiring 28 are formed as shown in FIG. 5G.

According to the manufacturing method of the present embodiment asdescribed above, the diameter of the bottom of the contact hole 24 canbe enlarged without the silicon film 14 being exposed to the inside ofthe contact hole 24. Therefore, according to the manufacturing method ofthe present embodiment, a semiconductor device can stably bemanufactured which is low in contact resistance and provides stableoperating characteristics, in a manner similar to the first embodiment.

Fourth Embodiment

A forth embodiment of the present invention will next be explained withreference to FIGS. 6A through 6I. FIGS. 6A through 6E are identical toFIGS. 1A through 1E to which reference is made in the description of therelated art. Further, FIG. 6F is identical to FIG. 2 to which referenceis made to describe the problem which arises where the conventionalmethod and a process for enlarging a contact hole 24 are combined intoone.

Namely, according to the manufacturing method of the present embodiment,a contact hole 24, which reaches a semiconductor substrate 10, is firstdefined by the conventional manufacturing method (FIGS. 6A through 6E).

Next, the bottom of the contact hole 24 is scaled up by wet etching insuch a manner that an exposed portion 30 of a silicon film 14 is formed(FIG. 6F).

Next, a nitride film 34 is deposited inside the contact hole 24 and overan interlayer oxide film 20 with a thickness of from about 10 nm toabout 50 nm by a CVD method as shown in FIG. 6G. Incidentally, thenitride film 34 may be replaced by a nitride oxide film or a laminatedfilm of a nitride film and a nitride oxide film.

Next, the entire surface of the semiconductor wafer is etched back bydry etching such as a RIE method as shown in FIG. 6H. As a result, thenitride film 34 is removed from the surface of the interlayer oxide film20 and the bottom of the contact hole 24. Since the nitride film 34deposited on the side face of the contact hole 24 is not removed at thistime, the exposed portion 30 of the silicon film 14 is maintained in astate covered with the nitride film 34.

Next, a silicon film is deposited over the entire surface of thesemiconductor wafer so that the contact hole 24 is filled with silicon.The silicon film is polycrystalline silicon or amorphous silicon dopedwith P or As and has a thickness of 50 nm to 200 nm over the interlayeroxide film 20. The so-deposited silicon is patterned in each desiredshape by the dry etching such as the RIE method. As a result, a contactplug 26 and a wiring 28 are formed as shown in FIG. 6I.

According to the manufacturing method of the present embodiment asdescribed above, the silicon film 14 can be prevented from being exposedto the inside of the contact hole 24 while the diameter of the bottom ofthe contact hole 24 is being enlarged. Therefore, according to themanufacturing method of the present embodiment, a semiconductor devicecan stably be manufactured which is low in contact resistance andprovides stable operating characteristics, in a manner similar to theembodiments 1 through 3.

Since the diameter of the bottom of the contact hole 24 is enlarged asdescribed above in the present embodiment, a large contact area isensured between the contact plug 26 and the semiconductor substrate 10.Therefore, the manufacturing method according to the present embodimentis capable of sufficiently reducing a contact resistance between thecontact plug 26 and the semiconductor substrate 10 and effectivelypreventing the occurrence of problems such as an increase in contactresistance, a reduction in drive capability of each transistor.

Fifth Embodiment

A fifth embodiment of the present invention will next be explained withreference to FIGS. 7, 8A through 8F and FIGS. 9A through 9F.

FIG. 7 is a plane view showing the structure of a memory cell of a DRAM.

As shown in FIG. 7, the memory cell of the DRAM is provided with activeregions 40 formed on the surface of a semiconductor substrate. Each ofthe active regions 40 includes an impurity layer (to be described later)which functions as a source-drain region of a transistor, and a channelregion which functions as a channel region of the transistor. Eachindividual active regions 40 are partitioned by trench isolations (to bedescribed later) on the semiconductor substrate.

A plurality of gate electrodes 42 are formed over the semiconductorsubstrate with predetermined intervals left therebetween. As shown inFIG. 7, there are formed between the two gate electrodes 42 and outsidethereof pad contact plugs 44, 46 and 48, which are conductive to theimpurity layer of each active region 40. The pad contact plug 44 isconductive to its corresponding bit line 52 through a bit line contactplug 50. On the other hand, the pad contact plugs 46 and 48 areconductive to their corresponding storage nodes 58 and 60 throughstorage node contact plugs 54 and 56.

The memory cell shown in FIG. 7 is characterized in that each of the bitlines 52 and the storage node contacts 54 and 56 have a structuresimilar to the first embodiment referred to above. A method ofmanufacturing the memory cell shown in FIG. 7 will be explained belowwith reference to FIGS. 8A through 9F.

FIGS. 8A through 9F are a series of cross-sectional views for describingthe method of manufacturing the memory cell shown in FIG. 7. In thesedrawings, those represented in the left row of the sheet (indicated byA, C or E) are cross-sectional views obtained by cutting the memory cellalong line A-A′ shown in FIG. 7, respectively. Drawings represented inthe right row of the sheet (indicated by B, D or F) are cross-sectionalviews obtained by cutting the memory cell along line B-B′ shown in FIG.7, respectively.

In the manufacturing method according to the present embodiment, trenchisolations 62 for partitioning each individual active regions are firstformed in the vicinity of the surface of the semiconductor substrate 10as shown in FIGS. 8A and 8B. Next, a gate oxide film 64 and a gateelectrode 42 are formed on the semiconductor substrate 10. The gateelectrode 42 comprises a silicon film 66, a silicon oxide film 68 and asilicon nitride film 70 respectively deposited by a reduced pressure CVDmethod.

The silicon film 66 included in the gate electrode 42 is a doped siliconfilm of polycrystalline silicon or amorphous silicon and contains animpurity such as P or As or the like. The silicon film 66 may bereplaced by, for example, a silicide film comprised of a high meltingpoint metal film such as Ti, TiN or W, a laminated film of the dopedsilicon film and the silicide film, or a conductive metal film such asW, Al.

In the manufacturing method according to the present embodiment, animpurity layer 72, which serves as a source-drain region of atransistor, is next formed on its corresponding active region of thesemiconductor substrate 10 as shown in FIG. 8B.

Next, a silicon nitride film is deposited over the entire surface of asemiconductor wafer by the reduced pressure CVD method. The entiresurface of the semiconductor wafer is etched back by dry etching such asa RIE method to thereby form sidewalls 74 for covering the side faces ofeach gate electrode 42 as shown in FIG. 8C.

Thereafter, a silicon nitride film 76 is deposited over the entiresurface of the semiconductor wafer by the reduced pressure CVD method asshown in FIGS. 8C and 8D.

Next, as shown in FIGS. 8E and 8F, an interlayer oxide film 78 dopedwith an impurity such as P or B is deposited over the entire surface ofthe semiconductor wafer by the reduced pressure or atmospheric CVD. Theinterlayer oxide film 78 is subjected to reflow processing to enhanceits embedding characteristics and flatness. Pad contact holes each ofwhich reaches the active region of the semiconductor substrate 10, aredefined in the interlayer oxide film 78 by a self-aligning manner.

Next, polycrystalline silicon or amorphous silicon doped with P or As isdeposited over the entire surface of the semiconductor wafer so thateach pad contact hole is filled with silicon. The so-deposited siliconis etched back by dry etching such as the RIE method to thereby form padcontact plugs 44 and 48 embedded in the interlayer oxide film 78.

Subsequently, bit lines 52, storage node contact plugs 54 or the likeare formed by applying the manufacturing method according to the firstembodiment.

Namely, when the pad contact plugs 44 and 48 are formed by theabove-described series of processes, an interlayer oxide film 12 and anitride film 32 are next formed over the interlayer oxide film 78 asshown in FIGS. 9A and 9B. In the interlayer oxide film 12 and thenitride film 32 is formed a bit line contact hole 80 opening up to thepad contact plug 44 at a predetermined position.

Thereafter, a silicon film 14 and a nitride film 16, which turn tocomponents of the bit line 52, are deposited over the nitride film 32 asshown in FIG. 9C. Further, the processing is put forward according tothe method of the first embodiment (see FIGS. 3A through 3H), whereby astorage node contact plug 54 (corresponding to the plug 26 and wiring 28employed in the first embodiment) conductive to its corresponding padcontact plug 48 is formed as shown in FIG. 9D.

According to the above-described manufacturing method, the bottom of thestorage node contact plug 54 can greatly be enlarged withoutshort-circuiting the silicon film 14 used as a wiring layer of each bitline 52 and the storage node contact plug 54. Therefore, according tothe manufacturing method of the present embodiment, the contactresistance between the storage node contact plug 54 and the pad contactplug 48 can be controlled low sufficiently without making a shortcircuit between each bit line 52 and the storage node contact plug 54.

In the present embodiment, a silicon nitride film 82 is next depositedover its corresponding interlayer oxide film 20 as shown FIG. 9E by thereduced pressure CVD. A silicon oxide film 84 doped with P or B isfurther deposited on the silicon nitride film 82 by the reduced pressureor atmospheric CVD.

Afterwards, a space for forming a storage node of each capacitor isdefined inside the silicon oxide film 84 by dry etching such as the RIEmethod as shown in FIG. 9F. A polycrystalline silicon film, amorphoussilicon film doped with P and As, or a laminated film of those films isformed within the space as a lower electrode 86 of the capacitor.

When the lower electrode 86 is composed of the amorphous silicon, amethod of charging an SiH₄ gas into a furnace to thereby apply thenuclei of Si to the surface of the silicon oxide film 84 and thereaftercharging a PH₃ gas therein and growing a Si crystal by executinghigh-temperature annealing is generally carried out. According to thismethod, the surface of the lower electrode 86 can be brought toconductive granular crystalline.

A capacitor insulating film 88 is deposited on the surface of the lowerelectrode 86. A so-called ON film obtained by subjecting the surface ofa silicon nitride film deposited by a CVD method to thermal oxidation ora Ta₂O₅ film is used as the capacitor insulating film 88. An upperelectrode 90 is deposited on the capacitor insulating film 88. When thecapacitor insulating film 88 is of the ON film, the upper electrode 90can be formed by depositing the polycrystalline or amorphous siliconfilm doped with P or As by the CVD method. On the other hand, when thecapacitor insulating film 88 is of the Ta₂O₅ film, the upper electrode90 can be formed of a high melting point metal film such as Ti, TiN.

Sixth Embodiment

A sixth embodiment of the present invention will next be described withreference to FIGS. 10A through 10D together with FIGS. 9A and 9B.

In a manufacturing method according to the present embodiment, thestructure shown in FIGS. 9A and 9B is manufactured according to aprocedure similar to the fifth embodiment. A bit line 52, a storage nodecontact plug 54, and the like are next formed by applying themanufacturing method according to the second embodiment.

Namely, in the present embodiment, a silicon film 14 and a nitride film16, which turn to components of the bit line 52, are deposited over anitride film 32 as shown in FIG. 10A after the bit line contact hole 80has been defined according to a technique similar to the fifthembodiment (FIGS. 9A and 9B). Further, the processing is put forwardaccording to the method of the second embodiment (see FIGS. 4A through4G) to thereby form sidewalls 18 extended downward from the bottom faceof the nitride film 32 as well as the storage node contact plug 54(corresponding to the plug 26 and wiring 28 employed in the secondembodiment) conductive to its corresponding pad contact plug 48 as shownin FIG. 10B.

According to the aforementioned manufacturing method, the bottom of thestorage node contact plug 54 can be enlarged on a large scale withoutshort-circuiting the silicon film 14 used as a wiring layer of the bitline 52 and the storage node contact plug 54. Further, according to themanufacturing method of the present embodiment, a large interval can beensured between the interlayer oxide film 78 and the silicon film 14whereby wiring capacitance in a memory cell is reduced to a sufficientdegree. Therefore, according to the manufacturing method of the presentembodiment, a DRAM, which exhibits excellent electrical characteristics,can stably be manufactured.

A lower electrode 86 of a capacitor, a capacitor insulating film 88, anupper electrode 90 thereof, and the like are subsequently formedaccording to a procedure similar to the fifth embodiment, whereby amemory cell structure shown in FIGS. 10C and 10D is implemented.

Seventh Embodiment

A seventh embodiment of the present invention will next be describedwith reference to FIGS. 11A through 11D together with FIGS. 9A and 9B.

In a manufacturing method according to the present embodiment, thestructure shown in FIGS. 9A and 9B is manufactured according to aprocedure similar to the fifth embodiment. A bit line 52, a storage nodecontact plug 54, and the like are next formed by applying themanufacturing method according to the third embodiment.

Namely, in the present embodiment, a silicon film 14 and a nitride film16, which turn to components of the bit line 52, are deposited over anitride film 32 as shown in FIG. 11A after a bit line contact hole 80has been defined according to a technique similar to the fifthembodiment (FIGS. 9A and 9B). Further, the processing is put forwardaccording to the method of the third embodiment (see FIGS. 5A through5G) to thereby form the nitride film 32 which exists only below thesilicon film 14 and below sidewalls 18 as well as a storage node contactplug 54 (corresponding to the plug 26 and wiring 28 employed in thethird embodiment) conductive to its corresponding pad contact plug 48 asshown in FIG. 11B.

According to the aforementioned manufacturing method, the bottom of thestorage node contact plug 54 can be enlarged on a large scale withoutshort-circuiting the silicon film 14 used as a wiring layer of the bitline 52 and the storage node contact plug 54. Therefore, according tothe manufacturing method of the present embodiment, the contactresistance between the storage node contact plug 54 and the pad contactplug 48 can be controlled low sufficiently without making a shortcircuit between each bit line 52 and the storage node contact plug 54.

A lower electrode 86 of a capacitor, a capacitor insulating film 88, anupper electrode 90 thereof, and the like are subsequently formedaccording to a procedure similar to the fifth embodiment, whereby amemory cell structure shown in FIGS. 11C and 11D is implemented.

Eighth Embodiment

An eighth embodiment of the present invention will next be describedwith reference to FIGS. 12A through 12F together with FIGS. 8E and 8F.

In a manufacturing method according to the present embodiment, thestructure shown in FIGS. 8E and 8F is manufactured according to aprocedure similar to the fifth embodiment. Then, a bit line 52, astorage node contact plug 54, and the like are formed by applying themanufacturing method according to the fourth embodiment.

Namely, in the present embodiment, pad contact plugs 44 and 48 areformed according to a technique similar to the fifth embodiment (FIGS.8E and 8F). Afterwards, an interlayer oxide film 12 is further formed onan interlayer oxide film 78 as shown in FIGS. 12A and 12B. Each bit linecontact hole 80 defined up to its corresponding pad contact plug 44 isdefined in the interlayer oxide film 12 in desired place.

Next, a silicon film 14 and a nitride film 16, which turn to componentsfor each bit line 52, are deposited over the interlayer oxide film 12 asshown in FIG. 12C. Further, the processing is put forward according tothe method of the fourth embodiment (see FIGS. 6A through 6I), whereby astorage node contact plug 54 (corresponding to the plug 26 and wiring 28employed in the fourth embodiment) conductive to its corresponding padcontact plug 48 is formed together with a nitride film 34 for coveringthe side of a storage node contact hole as shown in FIG. 12D.

According to the above-described manufacturing method, the bottom of theplug 54 can greatly be enlarged without short-circuiting the siliconfilm 14 used as a wiring layer of each bit line 52 and the storage nodecontact plug 54. Therefore, according to the manufacturing method of thepresent embodiment, the contact resistance between the storage nodecontact plug 54 and the pad contact plug 48 can be controlled lowsufficiently without making a short circuit between each bit line 52 andthe storage node contact plug 54.

Ninth Embodiment

A ninth embodiment of the present invention will next be described withreference to FIGS. 13 and 14.

FIG. 13 shows a cross sectional view of a memory cell, which is takenalong line A-A′ at the time that the etching step for defining the bitline contact hole 80 is started in the fifth embodiment. FIG. 14 shows across sectional view of a memory cell, which is taken along line A-A′ atthe time that similar etching is started in the present embodiment.

In the aforementioned fifth embodiment, etching for defining the bitline contact hole 80 is executed in a state in which the interlayeroxide film 12 is covered with the nitride film 32. In this case, thereis need to form an anti-reflection film 94 such as an organic ARC on thenitride film 32 for the purpose of patterning a photoresist 92 byphotolithography with enough accuracy.

In a manufacturing method according to the present embodiment, a plasmanitride film (p-SiON film) 96 containing oxygen is formed on theinterlayer oxide film 12 as an alternative to the nitride film 32 asshown in FIG. 14. The manufacturing method according to the presentembodiment is identical to the manufacturing method according to thefifth embodiment except for the above-described point.

The p-SiON film 96 is allowed to function as a stopper film in a mannersimilar to the nitride film 32 upon dry etching of a silicon oxide film.Further, the p-SiON film 96 can also be used as an anti-reflection filmupon photolithography. Therefore, according to the manufacturing methodof the present embodiment, a photo resist 92 can be patterned with highaccuracy without forming the anti-reflection film 94 on the p-SiON film96. For this reason, according to the manufacturing method of thepresent embodiment, a memory cell can be manufactured by fewer steps ascompared with the manufacturing method according to the fifthembodiment.

While the aforementioned ninth embodiment has described the case inwhich the p-SiON film 96 has been utilized in combination with themethod of the fifth embodiment, the manufacturing method usable incombination with the p-SiON film 96 is not limited to the method of thefifth embodiment. Namely, the p-SiON film 96 may be utilized incombination with the manufacturing method of the sixth or seventhembodiment.

Since the present invention is constructed in the above-describedmanner, the following advantageous effects are brought about.

According to a first aspect of the present invention, since the bottomface of a wiring is covered with a lower insulating film, noshort-circuit is developed between the wiring and a contact plug even ifa contact hole is provided with an enlarged portion. Further, accordingto the present invention, since the substantially entire surface of aninterlayer oxide film is covered with the lower insulating film, thewiring can effectively be prevented from being oxidized upon reflow ofthe interlayer oxide film. Therefore, the present invention implements asemiconductor device stable in characteristic.

According to a second aspect of the present invention, the bottom faceof each sidewall positions closer to a substrate layer than does thebottom face of a lower insulating film. Such a configuration ensures alarge interval between the substrate layer and wiring without causing anopening failure of a contact hole. Therefore, the present inventionimplements a semiconductor device with small wiring capacitance.

According to a third aspect of the present invention, the bottom face ofeach sidewall positions closer to a substrate layer than does the bottomface of a lower insulating film by 10 nm or more. Therefore, the presentinvention sufficiently reduces wiring capacitance lying within thesemiconductor device.

According to a fourth aspect of the present invention, a step developedbetween the bottom face of each sidewall and the bottom face of a lowerinsulating film is set to within 50 nm. Therefore, the present inventionefficiently reduces the wiring capacitance with a practical structure.

According to a fifth aspect of the present invention, a wiring exposedto the inside of a contact hole due to the enlargement of the contacthole can be covered with a short-circuit proof film. Therefore,according to the present invention, a short-circuit between the wiringand a contact plug can reliably be prevented even if no lower insulatingfilm is formed under the wiring.

According to a sixth aspect of the present invention, a short-circuitproof film can be formed of a nitride based insulating film which issuitable to easily ensure an enough etching selectivity with respect toa silicon oxide film.

According to a seventh aspect of the present invention, a lowerinsulating film, an upper insulating film, sidewalls or the like can beformed of a silicon nitride film which is suitable to easily ensure anenough etching selectivity with respect to a silicon oxide film.

According to a eighth aspect of the present invention, a lowerinsulating film, an upper insulating film, sidewalls or the like can beformed of a silicon nitride oxide film which is suitable to easilyensure an enough etching selectivity with respect to a silicon oxidefilm.

According to a ninth aspect of the present invention, advantageousresult of a reduction in contact resistance due to the scaling up of acontact hole can be implemented in a memory cell of a DRAM.

According to a tenth aspect of the present invention, the simplificationof steps can be achieved by using a lower insulating film as ananti-reflection film.

Further, the present invention is not limited to these embodiments, butvariations and modifications may be made without departing from thescope of the present invention.

What is claimed is:
 1. A semiconductor device having a contact holedefined between adjacent two wirings by a self-aligning manner,comprising: a contact plug formed in said contact hole; a substratelayer conductive to the bottom face of said contact plug; an interlayeroxide film formed on said substrate layer; a lower insulating filmformed of a nitride based insulating film so as to cover the entiresurface of said interlayer oxide film except for said contact holeportion; said two wirings formed on said lower insulating film with saidcontact hole interposed therebetween; an upper insulating film formed ofa nitride based insulating film with the same width as said each wiringso as to cover the upper surface of said each wiring; and sidewallsformed of a nitride based insulating film so as to cover the side facesof said each wiring and the side faces of said upper insulating film,wherein said contact hole has an enlarged portion formed in the samelayer as said interlayer oxide film, which has a diameter larger than aninterval defined between said two wirings.
 2. A semiconductor devicehaving a contact hole defined between adjacent two wirings by aself-aligning manner, comprising: a contact plug formed in said contacthole; a substrate layer conductive to the bottom face of said contactplug; an interlayer oxide film formed on said substrate layer; said twowirings formed in a layer above said interlayer oxide film with saidcontact hole interposed therebetween; a lower insulating film formed ofa nitride based insulating film between said interlayer oxide film andsaid each wiring with the same width as said each wiring; an upperinsulating film formed of a nitride based insulating film so as to coverthe upper surface of said each wiring with the same width as said eachwiring; and sidewalls formed of a nitride based insulating film so as tocover the side faces of said each wiring and the side faces of saidupper and lower insulating films, wherein said contact hole has adiameter larger than an interval defined between said two wirings withinthe same layer as said interlayer oxide film, and the bottom face ofsaid each sidewall is shifted toward said substrate layer by apredetermined length as compared with the bottom face of said lowerinsulating film.
 3. The semiconductor device according to claim 2,wherein said predetermined length is a value of 10 nm or more.
 4. Thesemiconductor device according to claim 3, wherein said predeterminedlength is a value of 50 nm or less.
 5. A semiconductor device having acontact hole defined between adjacent two wirings by a self-aligningmanner, comprising: a contact plug formed in said contact hole; asubstrate layer conductive to the bottom face of said contact plug; aninterlayer oxide film formed on said substrate layer; said two wiringsformed on said interlayer oxide film with said contact hole interposedtherebetween; an upper insulating film formed of a nitride basedinsulating film so as to cover the upper surface of said each wiringwith the same width as said wiring; sidewalls formed of a nitride basedinsulating film so as to cover the side faces of said each wiring andthe side faces of said upper insulating film; and a short-circuit prooffilm formed of a single insulating material so as to cover the entireside face of said contact plug, wherein said contact hole has a diameterlarger than an interval defined between said two wirings within the samelayer as said interlayer oxide film.
 6. The semiconductor deviceaccording to claim 5, wherein said short-circuit proof film is formed ofa nitride based insulating film.
 7. The semiconductor device accordingto claim 1, wherein said nitride based insulating film includes asilicon nitride film.
 8. The semiconductor device according to claim 2,wherein said nitride based insulating film includes a silicon nitridefilm.
 9. The semiconductor device according to claim 5, wherein saidnitride based insulating film includes a silicon nitride film.
 10. Thesemiconductor device according to claim 1, wherein said nitride basedinsulating film includes a silicon nitride oxide film.
 11. Thesemiconductor device according to claim 2, wherein said nitride basedinsulating film includes a silicon nitride oxide film.
 12. Thesemiconductor device according to claim 5, wherein said nitride basedinsulating film includes a silicon nitride oxide film.
 13. Thesemiconductor device according to claim 1, wherein said substrate layerincludes a gate electrode formed on a semiconductor substrate, aninterlayer insulating film for covering said gate electrode, and aplurality of pad contact plugs which extend through said interlayerinsulating film so as to be conductive to a source-drain region of saidsemiconductor substrate, said each wiring is a bit line formed over saidsubstrate layer; and said contact plug is a storage node contact plugwhich passes between said bit lines and is thereby conductive to one ofsaid plurality of pad contact plugs, and said semiconductor devicefurther comprising: a bit line contact plug which extends through saidlower insulating film and said interlayer oxide film to thereby bringsaid bit line and part of said plurality of pad contact plugs to aconducting state, and a capacitor formed on said storage node contactplug.
 14. The semiconductor device according to claim 2, wherein saidsubstrate layer includes a gate electrode formed on a semiconductorsubstrate, an interlayer insulating film for covering said gateelectrode, and a plurality of pad contact plugs which extend throughsaid interlayer insulating film so as to be conductive to a source-drainregion of said semiconductor substrate, said each wiring is a bit lineformed over said substrate layer; and said contact plug is a storagenode contact plug which passes between said bit lines and is therebyconductive to one of said plurality of pad contact plugs, and saidsemiconductor device further comprising: a bit line contact plug whichextends through said lower insulating film and said interlayer oxidefilm to thereby bring said bit line and part of said plurality of padcontact plugs to a conducting state, and a capacitor formed on saidstorage node contact plug.
 15. The semiconductor device according toclaim 13, wherein said lower insulating film is a plasma nitride filmcontaining oxygen.
 16. The semiconductor device according to claim 14,wherein said lower insulating film is a plasma nitride film containingoxygen.
 17. The semiconductor device according to claim 5, wherein saidsubstrate layer includes a gate electrode formed on a semiconductorsubstrate, an interlayer insulating film for covering said gateelectrode, and a plurality of pad contact plugs which extend throughsaid interlayer insulating film so as to be conductive to a source-drainregion of said semiconductor substrate, said each wiring is a bit lineformed over said substrate layer; and said contact plug is a storagenode contact plug which passes between said bit lines and is therebyconductive to one of said plurality of pad contact plugs, and saidsemiconductor device further comprising: a bit line contact plug whichextends through said interlayer oxide film to thereby bring said bitline and part of said plurality of pad contact plugs to a conductingstate, and a capacitor formed on said storage node contact plug.